1. Field of the Invention
The present invention relates to a backside illumination semiconductor image sensor.
2. Discussion of the Related Art
FIG. 1 schematically illustrates the circuit of a photosensitive cell of an array of photosensitive cells of an image sensor. A charge transfer transistor TR, a precharge device, and a read device are associated with each photosensitive cell of the array. The precharge device is formed of an N-channel MOS transistor RST, interposed between a supply rail Vdd and a read node S. The read device is formed of the series connection of first and second N-channel MOS transistors SF and RD. The drain of transistor SF is connected to supply rail Vdd. The source of transistor RD is connected to an input terminal P of a processing circuit (not shown). The gate of read transistor SF, assembled as a source follower, is connected to read node S. The photosensitive cell comprises a photodiode D having its anode connected to reference supply rail GND and its cathode connected to node S via charge transfer transistor TR. Generally, the gate control signals of transistors RD, RST, and TR are provided by control circuits, not shown in FIG. 1, and may be provided to all the photosensitive cells of a same row of the cell array. It should be noted that a photodiode is always associated with a transfer transistor TR, but that there may exist a single precharge device and a single read device for a group of photodiodes, the drains of the transfer transistors of these photodiodes being then interconnected to a same node S.
Read nodes of the photosensitive cell of FIG. 1 are well known and an example taken hereafter will be found in U.S. Pat. No. 7,067,792 (B5666).
FIG. 2 shows an example of a timing diagram of signals RD, RST, TR applied to the gates of the transistors of same reference and of voltage VS at node S of the circuit of FIG. 1 for a read cycle. Signals RD, RST, and TR are binary signals varying between high and low levels which may be different for each of the signals.
Between two read cycles of the photosensitive cell, signal TR is at the low level and the transfer transistor is off. An illumination causes the forming and the storage of charges at the level of photodiode D. Further, signal RST is in a high state. The precharge transistor is thus on. Voltage VS is then substantially equal to voltage Vdd.
At a time t0, the array row containing the photosensitive cell to be read is selected by setting signal RD to the high level. The precharge of read node S is interrupted by setting signal RST to the low state at a time t1, thus turning off the precharge transistor. Voltage VS at read node S is then set to a precharge level VRST which may be lower than voltage Vdd due to a coupling with precharge transistor RST. Precharge level VRST is generally disturbed by noise essentially originating from the thermal noise of the channel of the precharge transistor. This noise is sampled and maintained on the capacitance of node S during the off state of the precharge transistor. Precharge level VRST is then stored outside of the photosensitive cell by the read circuit.
At a time t2, signal TR is set to the high state. The transfer transistor is then on, which enables to transfer the charges stored in photodiode D towards read node S. Voltage VS then decreases down to a useful signal level VRD. Once the charge transfer has been performed, signal TR is set to a low level at a time t3, thus enabling to insulate photodiode D again and to start a new charge generation and storage cycle resulting from the illumination. The level of useful signal VRD is then read by the read circuit. Like precharge level VRST, useful signal level VRD is especially disturbed by the thermal noise of the precharge transistor which has been sampled and maintained on the capacitance of node S. The subtraction of signals VRD and VRST by the processing circuit enables eliminating the noise by double correlated sampling. Once the reading is over, signal RST is set to the high state at a time t4 to precharge read node S again. Finally, at a time t5, signal RD is set to the low state to deselect the photosensitive cell.
FIG. 3 illustrates, in partial simplified cross-section view, a monolithic embodiment of the assembly of diode D and of transfer transistor TR of FIG. 1. These elements are formed in the same active area of a semiconductor substrate 1 of a first conductivity type, for example, type P, lightly doped (P−). This substrate for example corresponds to an epitaxial layer on a silicon wafer which forms reference supply rail GND. The active area is delimited by field insulation areas 2, for example, made of silicon oxide (SiO2), and corresponds to a well 3 of the same conductivity type as underlying substrate 1, but more heavily doped. An insulated gate structure 4 that may be provided with lateral spacers is formed above the surface of well 3. Source and drain regions 5 and 6 of the opposite conductivity type, for example, N, are located on either side of gate 4, at the surface of well 3. Drain region 6, to the right of gate 4, is heavily doped (N+). Source region 5 is made on a much greater surface than drain region 6 and forms with underlying well 3 the junction of photodiode D. Gate 4 and drain 6 are solid with metallizations (not shown) which enable to put these regions in contact with transfer control signal TR and with the gate of transistor SF (node S), respectively. The structure is completed by heavily-doped P-type regions 8 and 9 (P+). Regions 8 and 9, which underlie areas 2, are connected to the reference voltage or ground via well 3 and substrate 1. Photodiode D is of so-called fully depleted type and comprises, at the surface of its source 5, a shallow P-type region 7, more heavily doped (P+) than well 3. Region 7 is in lateral (vertical) contact with region 8. It is thus permanently maintained at the reference voltage level.
An interconnect stack is formed on the upper surface or front surface of the structure. The light reaching the photodiodes arrives on the side of the interconnect stack and needs to cross a succession of insulating layers of this stack while the positions of the metal portions of the stack need to be selected to avoid hindering the light propagation. This poses various problems and backside illumination (BSI) devices have been provided in which the device is thinned down on its rear surface side and used so that the light reaches the photodiodes from this rear surface, that is, from the side opposite to the side on which the interconnect stack is formed. In such BSI devices, it is generally not necessary to associate one microlens with each pixel.
There exist many variations of frontside illumination and backside illumination structures. A common point of many of these structures is, as shown in FIG. 3, that the transfer transistor takes up a given silicon surface area in addition to the surface area taken up by the precharge and read devices. Thus, the useful photoconversion surface area is limited by the surface area necessary to position the transfer transistor and the precharge and read devices. In other words, for a given cell surface area, the surface necessary to place the various transistors associated with the cell needs to be added to the surface area taken up by the photoconversion diode.
Another problem of some prior art devices is the charge collection, that is, the transfer of the charges created in the photoconversion area towards the surface (generally the cathode of a diode) from which these charges need to be transferred.
Another problem of some prior art devices is the existence of non-negligible dark currents.
Another problem of some prior art devices lies in the impossibility of storing a large number of charges in each photoconversion period, which especially causes saturation problems.